SH7014 datasheet(249/754 Pages) RENESAS

249 / 754 page

10. Multifunction Timer Pulse Unit (MTU)

Rev.5.00 Sep. 27, 2007 Page 215 of 716

REJ09B0398-0500

Channels 1, 2: TIER1, TIER2

Bit:

TTGE

⎯

TCIEU

TCIEV

⎯

TGIEB

TGIEA

Initial value:

R/W:

R/W

Bit 7

⎯A/D Conversion Start Request Enable (TTGE): Enables or disables generation of an

A/D conversion start request by a TGRA register input capture/compare-match.

Bit 7

TTGE

Description

Disable A/D conversion start requests

(initial value)

Enable A/D conversion start request generation

Bit 6

⎯Reserved: This bit always read as 1. The write value should always be 1.

Bit 5

⎯Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests when the

underflow flag (TCFU) of the channel 1, 2 timer status register (TSR) is set to 1.

This bit is reserved for channel 0. It always reads as 0. The write value should always be 0.

Bit 5

TCIEU

Description

Disable UDF interrupt requests (TCIU)

(initial value)

Enable UDF interrupt requests (TCIU)

Bit 4

⎯Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests when the

overflow flag TCFV of the timer status register (TSR) is set to 1.

Bit 4

TCIEV

Description

Disable TCFV interrupt requests (TCIV)

(initial value)

Enable TCFV interrupt requests (TCIV)

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