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SH7059 Datasheet(PDF) 55 Page - Renesas Technology Corp |
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SH7059 Datasheet(HTML) 55 Page - Renesas Technology Corp |
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55 / 1042 page  Differences between SH7058 and SH7058S/SH7059 Rev.3.00 Mar. 12, 2008 Page lv of xc REJ09B0177-0300 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.6.3 Error Protection Figure 23.16 Transitions to and from Error Protection State 883, 884 • When the relevant bank area of flash memory is read during programming/erasing (including a vector read or an instruction fetch) • When a SLEEP instruction (including software standby mode) is executed during programming/erasing Error protection is cancelled (FLER bit is cleared) only by a power-on reset or in hardware standby mode. Note that the reset signal should only be released after providing a reset input over a period longer than the normal 100 μs. Reset or standby (Hardware protection) Program mode Erase mode Error protection mode Error protection mode (Software standby) Read disabled Programming/erasing enabled FLER=0 Read enabled Programming/erasing disabled FLER=0 Read enabled Programming/erasing disabled FLER=1 Read disabled Programming/erasing disabled FLER=1 RES = 0 or HSTBY = 0 Error occurred Error occurred (Software stan dby) RES =0 or HSTBY =0 Software standby mode Cancel software standby mode RES=0 or HSTBY=0 Programming/erasing interface register is in its initial state. Programming/erasing interface register is in its initial state. 25.6.3 Error Protection Figure 25.16 Transitions to and from Error Protection State Description amended • Flash memory is read during programming/erasing (including a vector read or an instruction fetch) • When a SLEEP instruction is executed during programming/erasing Error protection is cancelled (FLER bit is cleared) by a power-on reset, in software standby mode, or in hardware standby mode. Note that the reset signal should only be released after providing a reset input over a period longer than the normal 100 μs. Figure amended Reset or standby (Hardware protection) Program mode Erase mode Error protection mode (Software standby) Read disabled Programming/erasing enabled FLER=0 Read enabled Programming/erasing disabled FLER=0 Read enabled Programming/erasing disabled FLER=1 Read disabled Programming/erasing disabled FLER=undefined RES = 0 or HSTBY = 0 Error occurred Error occurred (Software stan dby) RES =0 or HSTBY =0 Software standby mode RES=0 , HSTBY=0 or software standby mode cancellation Programming/erasing interface register is in its initial state. The power is not supplied in this LSI. 23.7 Flash Memory Emulation in RAM Figure 23.18 Example of Overlapped RAM Operation 886 EB0 to EB15 H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 … H'FFFFF On-chip RAM H'FFFF0000 H'FFFF0FFF … H'FFFFBFFF 25.7 Flash Memory Emulation in RAM Figure 25.18 Example of Overlapped RAM Operation Address amended EB0 to EB15 H'000000 H'001000 H'002000 H'003000 H'004000 H'005000 H'006000 H'007000 H'008000 … H'17FFFF On-chip RAM H'FFFE8000 H'FFFEBFFF … H'FFFFBFFF |
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