SH7059 datasheet(97/1042 Pages) RENESAS

97 / 1042 page

1. Overview

Rev.3.00 Mar. 12, 2008 Page 7 of 948

REJ09B0177-0300

1.2

Block Diagram

ROM (flash)

1.5 MB (SH7059)

1.0 MB (SH7058S)

RAM

80 KB (SH7059)

48 KB (SH7058S)

DMAC

(4 channels)

SCI (5 channels)

CMT (2 channels)

AUD

H-UDI

HCAN (2 channels)

SSU* (2 channels)

ATU-II

A/D

converter

WDT

BSC

Interrupt

controller

Clock pulse

generator

Port/control signals

Port

Port/address signals

PH15/D15

PH14/D14

PH13/D13

PH12/D12

PH11/D11

PH10/D10

PH9/D9

PH8/D8

PH7/D7

PH6/D6

PH5/D5

PH4/D4

PH3/D3

PH2/D2

PH1/D1

PH0/D0

PA0/TI0A

PA1/TI0B

PA2/TI0C

PA3/TI0D

PA4/TIO3A

PA5/TIO3B

PA6/TIO3C

PA7/TIO3D

PA8/TIO4A/ADTO0A

PA9/TIO4B/ADTO0B

PA10/TIO4C/ADTO1A

PA11/TIO4D/ADTO1B

PA12/TIO5A

PA13/TIO5B

PA14/TxD0/SSO0

PA15/RxD0/SSI0

PB0/TO6A

PB1/TO6B

PB2/TO6C

PB3/TO6D

PB4/TO7A/TO8A

PB5/TO7B/TO8B

PB6/TO7C/TO8C

PB7/TO7D/TO8D

PB8/TxD3/TO8E

PB9/RxD3/TO8F

PB10/TxD4/HTxD0/TO8G

PB11/RxD4/HRxD0/TO8H

PB12/TCLKA/

UBCTRG

PB13/SCK0/SSCK0

PB14/SCK1/TCLKB/TI10

PB15/PULS5/SCK2/SSCK1

PC0/TxD1

PC1/RxD1

PC2/TxD2/SSO1

PC3/RxD2/SSI1

PC4/

IRQ0

PG0/PULS7/HRxD0/HRxD1

PG1/

IRQ1

PG2/

IRQ2/ADEND

PG3/

IRQ3/ADTRG0

PD0/TIO1A

PD1/TIO1B

PD2/TIO1C

PD3/TIO1D

PD4/TIO1E

PD5/TIO1F

PD6/TIO1G

PD7/TIO1H

PD8/PULS0

PD9/PULS1

PD10/PULS2

PD11/PULS3

PD12/PULS4

PD13/PULS6/HTxD0/HTxD1

PL0/TI10

PL1/TIO11A/

IRQ6

PL2/TIO11B/

IRQ7

PL3/TCLKB

PL4/

ADTRG0

PL5/

ADTRG1

PL6/ADEND

SSCK1/PL7/SCK2

PL8/SCK3

PL9/SCK4/

IRQ5

PL10/HTxD0/HTxD1/HTxD0 & HTxD1

PL11/HRxD0/HRxD1/HRxD0 & HRxD1

SCS0/PL12/IRQ4

SCS1/PL13/IRQOUT

EXTAL

XTAL

PLLVCC

PLLVSS

PLLCAP

Vcc (

×8)

PVcc1 (

×4)

PVcc2 (

×6)

VCL(

×3)

Vss (

×21)

AVref (

×2)

AVcc (

×2)

AVss (

×2)

AN31–0

AUDRST

AUDMD

AUDATA3–0

AUDCK

AUDSYNC

TMS

TRST

TDI

TDO

TCK

RES

HSTBY

FWE

MD2

MD1

MD0

NMI

WDTOVF

: Peripheral address bus (19 bits)

: Peripheral data bus (16 bits)

: Internal address bus (32 bits)

: Internal upper data bus (16 bits)

: Internal lower data bus (16 bits)

Note: * SSU: Synchronous Serial Communication Unit

CPU

FPU

Multiplier

Figure 1.1 Block Diagram

SH7059 Datasheet(PDF) 97 Page - Renesas Technology Corp

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