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SH7059 Datasheet(PDF) 30 Page - Renesas Technology Corp

Part # SH7059
Description  32-Bit RISC Microcomputer
PDF  1042 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7059 Datasheet(HTML) 30 Page - Renesas Technology Corp

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Differences between SH7058 and SH7058S/SH7059
Rev.3.00 Mar. 12, 2008 Page xxx of xc
REJ09B0177-0300
SH7058 (Rev.3, REJ09B0046-0300H)
SH7058S/SH7059
21.1 Overview
Table 21.1 SH7058 Multiplex Pins
739 - 741, 743
Function 1
(Related Module)
Function 2
(Related Module)
Function 3
(Related Module)
Function 4
(Related Module)
PA14 input/output (port)
TxD0 output (SCI)
PA15 input/output (port)
RxD0 input (SCI)
PB13 input/output (port)
SCK0 input/output (SCI)
PB15 input/output (port)
PULS5 output (APC)
SCK2 input/output (SCI)
PC2 input/output (port)
TxD2 output (SCI)
PC3 input/output (port)
RxD2 input (SCI)
PF14 input/output (port)
BACK output (BSC)
PF15 input/output (port)
BREQ input (BSC)
PL7 input/output (port)
SCK2 input/output (SCI)
PL12 input/output (port)
IRQ4 input (INTC)
PL13 input/output (port)
IRQOUT output (INTC)
IRQOUT output (INTC)
22.1 Overview
Table 22.1 SH7059 Multiplex Pins
Table amended
Function 1
(Related Module)
Function 2
(Related Module)
Function 3
(Related Module)
Function 4
(Related Module)
PA14 input/output (port)
TxD0 output (SCI)
SSO0 output (SSU)
PA15 input/output (port)
RxD0 input (SCI)
SSI0 input (SSU)
PB13 input/output (port)
SCK0 input/output (SCI)
SSCK0 output (SSU)
PB15 input/output (port)
PULS5 output (APC)
SCK2 input/output (SCI)
SSCK1 output (SSU)
PC2 input/output (port)
TxD2 output (SCI)
SSO1 output (SSU)
PC3 input/output (port)
RxD2 input (SCI)
SSI1 input (SSU)
PF14 input/output (port)
BACK output (BSC)
SCS0 input/output (SSU)
PF15 input/output (port)
BREQ input (BSC)
SCS1 input/output (SSU)
PL7 input/output (port)
SCK2 input/output (SCI)
SSCK1 output (SSU)
PL12 input/output (port)
IRQ4 input (INTC)
SCS0 input/output (SSU)
PL13 input/output (port)
IRQOUT output (INTC)
IRQOUT output (INTC)
SCS1 input/output (SSU)
21.3.1 Port A IO Register (PAIOR)
745
Bits PA15IOR to PA0IOR correspond to pins PA15/RxD0
to PA0/TI0A. PAIOR is enabled when port A pins function
as general input/output pins (PA15 to PA0) or ATU-II
input/output pins, and disabled otherwise.
…When port A pins function as PA15 to PA0 or ATU-II
input/output pins, a pin becomes an output when the
corresponding bit in PAIOR is set to 1, and an input when
the bit is cleared to 0.
PAIOR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode
or sleep mode.
22.3.1 Port A IO Register (PAIOR)
Description amended
Bits PA15IOR to PA0IOR correspond to pins
PA15/RxD0/SSI0 to PA0/TI0A. PAIOR is enabled when
port A pins function as general input/output pins (PA15 to
PA0), ATU-II input/output pins or transmit/receive
input/output for the SSU (SSI0 and SSO0), and disabled
otherwise.
…When port A pins function as PA15 to PA0, ATU-II
input/output pins or transmit/receive input/output for the
SSU (SSI0 and SSO0), a pin becomes an output when the
corresponding bit in PAIOR is set to 1, and an input when
the bit is cleared to 0.
PAIOR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), in hardware standby
mode, and in software standby mode. It is not initialized in
sleep mode.
21.3.2 Port A Control Registers H and L (PACRH, PACRL)
746
PACRH and PACRL are initialized to H'0000 by a power-on
reset (excluding a WDT power-on reset), and in hardware
standby mode. They are not initialized in software standby
mode or sleep mode.
22.3.2 Port A Control Registers H and L (PACRH, PACRL)
Description amended
PACRH and PACRL are initialized to H'0000 by a power-on
reset (excluding a WDT power-on reset), in hardware
standby mode, and in software standby mode. They are
not initialized in
sleep mode.



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