SH7059 datasheet(32/1042 Pages) RENESAS

32 / 1042 page

Differences between SH7058 and SH7058S/SH7059

Rev.3.00 Mar. 12, 2008 Page xxxii of xc

REJ09B0177-0300

SH7058 (Rev.3, REJ09B0046-0300H)

SH7058S/SH7059

21.3.4 Port B Control Registers H and L (PBCRH, PBCRL)

751, 752

PBCRH and PBCRL are initialized to H'0000 by a power-on

reset (excluding a WDT power-on reset), and in hardware

standby mode. They are not initialized in software standby

mode or sleep mode.

Port B Control Register H (PBCRH)

Bit:

PB15

MD1

—

PB13

Initial value:

R/W:

R/W

• Bits 15 and 14—PB15 Mode Bits 1 and 0 (PB15MD1,

PB15MD0): These bits select the function of pin

PB15/PULS5/SCK2.

Bit 15: PB15MD1

Bit 14: PB15MD0

Description

Reserved (Do not set)

• Bit 11—Reserved: This bit is always read as 0. The

write value should always be 0.

• Bit 10—PB13 Mode Bit (PB13MD): Selects the function

of pin PB13/SCK0.

Bit 10: PB13MD

Description

General input/output (PB13)

(Initial value)

Serial clock input/output (SCK0)

22.3.4 Port B Control Registers H and L (PBCRH, PBCRL)

Description amended

PBCRH and PBCRL are initialized to H'0000 by a power-on

reset (excluding a WDT power-on reset), in hardware

standby mode and in software standby mode. They are not

initialized in

sleep mode.

Port B Control Register H (PBCRH)

Bit:

PB15

MD1

PB13

MD1

PB13

MD0

Initial value:

R/W:

R/W

• Bits 15 and 14—PB15 Mode Bits 1 and 0 (PB15MD1,

PB15MD0): These bits select the function of pin

PB15/PULS5/SCK2/SSCK1.

Bit 15: PB15MD1

Bit 14: PB15MD0

Description

Serial clock output (SSCK1)

• Bits 11 and 10—PB13 Mode Bit 1,0 (PB13MD1,

PB13MD0): Selects the function of pin

PB13/SCK0/SSCK0.

Bit 11: PB13MD1

Bit 10: PB13MD0

Description

General input/output (PB13)

(Initial value)

Serial clock input/output (SCK0)

Serial clock output (SSCK0)

Reserved (Do not set)

21.3.5 Port B Invert Register (PBIR)

756

Bits PB15IR to PB13IR and PB11IR to PB0IR correspond

to pins PB15/PULS5/SCK2 to PB13/SCK0 and

PB11/RxD4/HRxD0/TO8H to PB0/TO6A. PBIR is enabled

when port B pins function as ATU-II outputs or serial clock

pins, and disabled otherwise.

…PBIR is initialized to H'0000 by a power-on reset

(excluding a WDT power-on reset), and in hardware

standby mode. It is not initialized in software standby mode

or sleep mode.

22.3.5 Port B Invert Register (PBIR)

Description amended

Bits PB15IR to PB13IR and PB11IR to PB0IR correspond

to pins PB15/PULS5/SCK2/SSCK1 to PB13/SCK0/SSCK0

and PB11/RxD4/HRxD0/TO8H to PB0/TO6A. PBIR is

enabled when port B pins function as ATU-II outputs or

serial clock pins, and disabled otherwise.

…PBIR is initialized to H'0000 by a power-on reset

(excluding a WDT power-on reset), in hardware standby

mode, and in software standby mode. It is not initialized in

sleep mode.

SH7059 Datasheet(PDF) 32 Page - Renesas Technology Corp

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