SH7059 datasheet(7/1042 Pages) RENESAS

7 / 1042 page

Rev.3.00 Mar. 12, 2008 Page vii of xc

REJ09B0177-0300

Differences between SH7058 and SH7058S/SH7059

SH7058 (Rev.3, REJ09B0046-0300H)

SH7058S/SH7059

All

Synchronous serial communication unit (SSU) added

1.1 Features

Table 1.1 SH7058 Features

3,4

Clock pulse generator (CPG/PLL)

• On-chip clock-multiplication PLL circuit (x 4, x 8)

Interrupt controller (INTC)

• 117 internal interrupt sources

(ATU-II x 75, SCI x 20, DMAC x 4, A/D x 5, WDT x 1, UBC

x 1, CMT x 2, HCAN-II x 8, H-UDI x 1)

Direct memory access controller (DMAC) (4 channels)

• DMA transfer requests by on-chip modules

⎯ SCI, A/D converter, ATU-II, HCAN-II

Advanced user debugger (AUD)

• RAM monitor mode

⎯ Data input/output frequency: 10 MHz or less

1.1 Features

Table 1.1 SH7059 Features

CPG/PLL, INTC, DMAC, and AUD amended

Clock pulse generator (CPG/PLL)

• On-chip clock-multiplication PLL circuit ( x 8)

Interrupt controller (INTC)

• 123 internal interrupt sources

(ATU-II x 75, SCI x 20, DMAC x 4, A/D x 5, WDT x 1, UBC

x 1, CMT x 2, HCAN-II x 8, H-UDI x 1, SSU x 6)

Direct memory access controller (DMAC) (4 channels)

• DMA transfer requests by on-chip modules

⎯ SCI, A/D converter, ATU-II, HCAN-II, SSU

Synchronous serial communication unit (SSU) (2 channels)

• Support for master mode

• Synchronous serial communications with devices

having a different clock phase or polarity

• Choice of 8/16/32-bit width of transmit/receive data

• Full-duplex communication capability

• Continuous serial communications

• Choice of LSB-first or MSB-first transfer

• Choice of clock source from among seven internal

clocks

• Five interrupt sources

Advanced user debugger (AUD)

• RAM monitor mode

⎯ Data input/output frequency: 1/8 or less of the

internal operating frequency (

φ)

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