SH7059 datasheet(22/1042 Pages) RENESAS

22 / 1042 page

Differences between SH7058 and SH7058S/SH7059

Rev.3.00 Mar. 12, 2008 Page xxii of xc

REJ09B0177-0300

SH7058 (Rev.3, REJ09B0046-0300H)

SH7058S/SH7059

Figure 15.8 Sample Flowchart for Receiving Serial Data (2)

498

Break?

Framing error handling

Clear RE bit in SCR to 0

Yes

Figure 15.8 Sample Flowchart for Receiving Serial Data (2)

Figure amended and note added

Break?

Framing error handling

Clear RE bit in SCR to 0

Yes

Note: Do not write to SMR, SCR, BRR, or SDCR between

the start and the end of a receive operation. However, this

does not apply to operation 5.

15.3.3 Multiprocessor Communication

Transmitting Multiprocessor Serial Data:

Figure 15.11 Sample Flowchart for Transmitting

Multiprocessor Serial Data

502

Clear TE bit in SCR to 0;

select theTxD pin function as

an output port with the PFC

15.3.3 Multiprocessor Communication

Transmitting Multiprocessor Serial Data:

Figure 15.11 Sample Flowchart for Transmitting

Multiprocessor Serial Data

Figure amended and note added

Clear TE bit in SCR to 0;

select theTxD pin function as

an output port with the PFC

Note: Do not write to SMR, SCR, BRR, or SDCR between

the start and the end of a transmit operation. However, this

does not apply to operation 5.

Receiving Multiprocessor Serial Data:

Figure 15.13 Sample Flowchart for Receiving

Multiprocessor Serial Data (1)

504

Clear RE bit in SCR to 0

Receiving Multiprocessor Serial Data:

Figure 15.13 Sample Flowchart for Receiving

Multiprocessor Serial Data (1)

Figure amended and note added

Clear RE bit in SCR to 0

Note: Do not write to SMR, SCR, BRR, or SDCR between

the start and the end of a receive operation. However, this

does not apply to operation 6.

Figure 15.14 Sample Flowchart for Receiving

Multiprocessor Serial Data (2)

505

Framing error handling

Clear RE bit in SCR to 0

Figure 15.14 Sample Flowchart for Receiving

Multiprocessor Serial Data (2)

Figure amended and note added

Framing error handling

Clear RE bit in SCR to 0

Note: Do not write to SMR, SCR, BRR, or SDCR between

the start and the end of a receive operation. However, this

does not apply to operation 6.

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