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7641 Datasheet(PDF) 194 Page - Renesas Technology Corp |
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7641 Datasheet(HTML) 194 Page - Renesas Technology Corp |
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194 / 385 page  Rev.2.00 Aug 28, 2006 page 63 of 148 7641 Group REJ09B0336-0200 APPLICATION 2.4 UART (2) Setting examples using SCSGCLK output Table 2.4.2 shows setting examples of the SCSG1, SCSG2 and the baud rate generator (BRG) values and transfer bit rate values. Table 2.4.2 Setting examples of SCSG1, SCSG2 and baud rate generator values and transfer bit rate values ( φφφφφ = 12 MHz)) Transfer bit rate (bps) (Note 1) 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 14400 19200 28800 31250 38400 57600 115200 SCSG1 setting value (Note 3) bypassed bypassed 78 (4E16) 172 (AC16) bypassed bypassed 24 (1816) bypassed 24 (1816) bypassed 24 (1816) 24 (1816) 24 (1816) 24 (1816) 24 (1816) 24 (1816) 35 (2316) 24 (1816) bypassed 35 (2316) bypassed 11 (0B16) SCSG2 setting value 149 (9516) 99 (6316) 67 (4316) 55 (3716) 49 (3116) 24 (1816) 11 (0B16) 24 (1816) 19 (1316) 24 (1816) 19 (1316) 19 (1316) 14 (0E6) 19 (1316) 14 (0E6) 09 (0916) 00 (0016) 00 (0016) bypassed 00 (0016) bypassed 00 (0016) SCSGCLK (Hz) (Note 4) 80000.00 120000.00 174236.78 213047.07 240000.00 480000.00 960000.00 480000.00 576000.00 480000.00 576000.00 576000.00 768000.00 576000.00 768000.00 1152000.00 11666666.66 11520000.00 12000000.00 11666666.66 12000000.00 11000000.00 UART clock prescaling (Note 2) 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 Real rate (bps) 50.00 75.00 110.00 134.50 150.00 300.00 600.00 1200.00 1800.00 2000.00 2400.00 3600.00 4800.00 7200.00 9600.00 14400.00 19188.60 28800.00 31250.00 38377.19 57692.31 114583.33 BRG setting value 99 (6316) 99 (6316) 98 (6216) 98 (6216) 99 (6316) 99 (6316) 99 (6316) 24 (1816) 19 (1316) 14 (0E6) 14 (0E6) 9 (0916) 9 (0916) 4 (0416) 4 (0416) 4 (0416) 37 (2516) 24 (1816) 23 (1716) 18 (1216) 12 (0C16) 5 (0516) Special Count Source Generator Notes 1: Equation of transfer bit rate: ✽ : fi is selectable among SCSGCLK/1, SCSGCLK/8, SCSGCLK/32, and SCSGCLK/256 with bits 1 and 2 of UARTx mode register. Transfer bit rate (bps) = (BRG setting value + 1) ✕ 16 fi✽ 2: Select the UART clock prescaling with bits 1 and 2 of UARTx mode register. 3: The internal clock φ is used as the SCSG2 count source when the SCSG1 count stop bit is “1” or the SCSG1 timer set value is “0016”. 4: Equation of SCSGCLK frequency: SCSGCLK (MHz) = φ ✕ (SCSG1 setting value + 1) SCSG1 setting value ✕ (SCSG2 setting value + 1) 1 |
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