7641 datasheet(195/385 Pages) RENESAS

195 / 385 page

Rev.2.00

Aug 28, 2006

page 64 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.4 UART

2.4.5 Operation of transmitting and receiving

(1) Transmit operation

•The transmit buffer empty flag (TBE) is set to “0” when the low-order byte of transmitted data is

written into the UARTx (x = 1, 2) transmit buffer register 1 in the condition of transmission enabled.

When using 9-bit character length, set the data into the UARTx transmit buffer register 2 (high-order

byte) first before the UARTx transmit buffer register 1 (low-order byte).

•If the transmit shift register is empty in the condition of CTS function disabled, the transmitted data

which is written into the UARTx (x = 1, 2) transmit buffer register 1 will be transferred to the transmit

shift register at the same time. When the TBE flag becomes “1”, the following data can be set to

the UARTx (x = 1, 2) transmit buffer. At this point, the UART transmit interrupt request occurs when

the transmit interrupt source select bit (TIS) is “0”.

•When the CTS function is enabled, the transmitted data is not transferred to the transmit shift

•The data is transmitted with the LSB first format. Once the transmission starts, it continues until the

last bit has been transmitted even though clearing the transmit enable bit (TEN) to “0” (disabled)

or inputting “H” to the CTSx pin.

•After completion of the last bit transmitting, if the TBE flag is “1”, or the TEN bit is “0” (disabled)

or “H” is input to the CTSx pin, the transmit complete flag (TCM) goes to “1”. At this point, the

UARTx transmit interrupt request occurs when the TIS bit is “1”.

(2) Receive operation

•The data is received with the LSB first format in the condition of reception enabled.

•When the stop bit is detected, the received data is transferred from the receive shift register to the

UARTx (x = 1, 2) receive buffer register. At the same time, if there is no error, the receive buffer

full flag (RBF) is set to “1” and the UARTx receive buffer full interrupt request occurs.

•If receive errors occur, the corresponding error flags of UARTx status register are set to “1” and the

UARTx summing error interrupt request occurs.

•The receive buffer full flag (RBF) is set to “0” when the contents of UARTx receive buffer register

1 is read out. Then when the RTS function is disabled, the following data can be received.

When using 9-bit character length, read the data from the UARTx receive buffer register 2 (high-

order byte) first before the UARTx receive buffer register 1 (low-order byte).

•When the RTS function is enabled, the RTS assertion delay count is specified by the UARTx RTS

control register. The delay time from the reception of the last stop bit to the start bit is selectable.

The RTSx pin (P87/RTS1, P83/RTS2/STXD) outputs “H” during the delayed time. After that, the RTSx

pin outputs “L” and a reception is enabled.

•If the start bit is detected in the term of “H” assertion of RTS, its assertion count is suspended and

the RTSx pin remains “H” output. After receiving the last stop bit, the count is resumed.

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