7641 datasheet(196/385 Pages) RENESAS

196 / 385 page

Rev.2.00

Aug 28, 2006

page 65 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.4 UART

(3) Countermeasure for errors

Three errors can be detected at reception. Each error is detected simultaneously when the data is

transferred from the receive shift register to the receive buffer register. If receive errors occur, the

corresponding error flags of UARTx status register are set to “1”. When any one of errors occurs,

the summing error flag is set to “1” and the UARTx summing error interrupt request bit is also set

to “1”. If a receive error occurs, the reception does not set the UARTx receive buffer full interrupt

request bit to “1”.

If receive errors occur, initialize the error flags and the UARTx receive buffer register and then

retransmit the data.

Table 2.4.3 shows the error flags set condition and how to clear error flags.

Error flag set condition

•If the previous data in the receive buffer register

is not read before the current receive operation

is completed.

•If any one of error flags is “1” for the previous

data and the current receive operation is

completed.

•When the number of stop bit of the received

data does not correspond with the selection

with the stop bit length select bit (STB).

•When the sum total of 1s of received data and

the parity does not correspond with the selection

with the parity select bit (PMD).

•When any one of the PER, FER and OER is

set to “1”.

Error flag

Overrun flag (OER)

How to clear error flag

•Reading UARTx status register

•Hardware reset

•Setting the receive initialization bit

(RIN) to “1”

Table 2.4.3 Error flags set condition and how to clear error flags

Framing error flag

(FER)

Parity error flag (PER)

Summing error flag

(SER)

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