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7641 Datasheet(PDF) 200 Page - Renesas Technology Corp |
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7641 Datasheet(HTML) 200 Page - Renesas Technology Corp |
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200 / 385 page ![]() Rev.2.00 Aug 28, 2006 page 69 of 148 7641 Group REJ09B0336-0200 APPLICATION 2.4 UART Fig. 2.4.17 Registers setting for receiver (2) U2STS b0 b7 U2TRB1 U2TRB2 b0 b7 b0 b7 UART2 transmit/receive buffer register 2 (Address : 3D16) high-order 1 bit of receiving data read low-order 8 bits of receiving data read UART2 status register (Address : 3A16) Read data from high-order address first, then from low-order address. UART2 transmit/receive buffer register 1 (Address : 3C16) Receive buffer full flag Parity error flag Framing error flag Overrun error flag Summing error flag |
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