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7641 Datasheet(PDF) 201 Page - Renesas Technology Corp |
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7641 Datasheet(HTML) 201 Page - Renesas Technology Corp |
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201 / 385 page  Rev.2.00 Aug 28, 2006 page 70 of 148 7641 Group REJ09B0336-0200 APPLICATION 2.4 UART Figure 2.4.18 shows a control procedure of transmitter, and Figure 2.4.19 shows a control procedure of receiver. 10 ms pass ? Y N The second byte of a transmission data 1 0 U1STS (Address : 3216), bit0? 1 0 U1TRB2 (Add. : 3516) U1TRB1 (Add. : 3416) The first byte of a transmission data 1 0 • An interval of 10 ms generated by Timer • Transmission data write Transmit buffer empty flag is set to “0” by this writing. Transmission starts owing to “L” input to CTS pin. • Judgment of transferring data from Transmit buffer register to Transmit shift register (Transmit buffer empty flag) • Judgment of transferring data from Transmit buffer register to Transmit shift register (Transmit buffer empty flag) • Judgment of shift completion of Transmit shift register (Transmit complete flag) U1STS (Address : 3216), bit1? U1TRB2 (Add. : 3516) U1TRB1 (Add. : 3416) • Transmission data write Transmit buffer empty flag is set to “0” by this writing. U1STS (Address : 3216), bit1? RESET (Address : 3116) (Address : 3316), bit2 (Address : 3316), bit4 (Address : 3016) (Address : 3316), bit5 (Address : 3316), bit1 Initialization U1BRG U1CON U1CON U1MOD U1CON U1CON 1916 12 x 100x00002 1 1 q x: This bit is not used here. Set it to “0” or “1” arbitrarily. ICONA CLI (Address : 0516), bit7 0 • φ as UART clock, Clock prescaling 1/1, 1 stop bit, Parity checking disabled, 9-bit character length • CTS function enabled • UART1 transmit interrupt disabled Fig. 2.4.18 Control procedure of transmitter |
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