7641 datasheet(336/385 Pages) RENESAS

336 / 385 page

Rev.2.00

Aug 28, 2006

page 57 of 108

7641 Group

REJ09B0336-0200

APPENDIX

3.5 Control registers

Clock control register

b7 b6 b5 b4 b3 b2 b1 b0

Clock control register

(CCR : address 1F16)

Name

Functions

At reset R W

0 : XCOUT oscillation drive is enabled.

(When XCIN oscillation is enabled.)

1 : XCOUT oscillation drive is disabled.

XCOUT oscillation drive

disable bit (CCR5)

0 : XOUT oscillation drive is enabled.

(When XIN oscillation is enabled.)

1 : XOUT oscillation drive is disabled.

XOUT oscillation drive

disable bit (CCR6)

XIN divider select bit

(CCR7) (Note)

Fix these bits to “0”.

Note: This bit is valid when (b7, b6 of CPMA) = “00”.

0 : f(XIN)/2 is used for the system clock.

1 : f(XIN) is used for the system clock.

Timer X (low, high)

b7 b6 b5 b4 b3 b2 b1 b0

Timer XL, Timer XH

(TXL, TXH: addresses 2016, 2116)

Functions

At reset R W

qTimer X’s count value is set through this register.

qWriting operation depends on the timer X write control bit.

When it is “0”, the values are simultaneously written into timer X

latch and counter.

When it is “1”, the values are written into only timer X latch.

qTimer X is a down-count timer.

qWhen reading this register’s address, the timer X’s count value is

read out.

Notes 1: Read and write operation to timer X must be performed for both high and low-order bytes.

2: When reading timer X, read the high-order byte first and then the low-order byte.

3: When writing to timer X, write the low-order byte first and then the high-order byte.

4: Do not read this register during the write operation, or do not write during the read operation.

Fig. 3.5.17 Structure of Clock control register

Fig. 3.5.18 Structure of Timer X

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