SH7713 datasheet(336/904 Pages) RENESAS

336 / 904 page

Section 10 Power-Down Modes

Rev.1.50 Aug. 30, 2006 Page 296 of 860

REJ09B0288-0150

Table 10.1

States of Power-Down Modes

State

Mode

Transition

Conditions

CPG

EtherC

E-DMAC CPU

CPU

Reg-

ister

On-Chip

Memory

On-Chip

Periphera

l Modules Pins

External

Memory

Canceling

Procedure

Sleep

mode

Execute SLEEP

instruction with

STBY bit cleared

to 0 in STBCR

Run

Halt

Held

Run

Held

Refreshed 1. Interrupt

2. Reset

Software

Standby

mode

Execute SLEEP

instruction with

STBY bit set to 1

in STBCR

Halt

Held

Halt*

Held

Self-

refreshed

1. Interrupt

2. Reset

Module

standby

function

Set MSTP bit to 1

in STBCR,

STBCR2, and

STBCR3

Run

Held

Specified

module

halts

Refreshed 1. Clear

MSTP bit

to 0

2. Power-on

reset

Notes: 1. The RTC runs when the START bit in RCR2 is set to 1. For details, see section 15,

Realtime Clock (RTC).

2. Depends on the on-chip peripheral modules. For details, see section 1, Overview and

Pin Function.

10.1.2

Reset

A reset is used at power-on or to re-execute from the initial state. This LSI supports two types of

reset: power-on reset and manual reset. In power-on reset, any processing to be currently executed

is terminated and any events not executed are canceled to execute reset processing immediately. In

manual reset, processing required to maintain external memory contents is continued. The

following shows the conditions in which power-on reset or manual reset occurs.

• Power-on reset

1. A low level signal is input to the

RESETP pin.

2. The WDT counter overflows if the WDT starts counting while the WT/

IT and RSTS bits in

WTCSR are set to 1 and cleared to 0, respectively.

3. An H-UDI reset occurs. (For details on the H-UDI reset, refer to section 22, User

Debugging Interface (H-UDI).)

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