SH7713 datasheet(340/904 Pages) RENESAS

340 / 904 page

Section 10 Power-Down Modes

Rev.1.50 Aug. 30, 2006 Page 300 of 860

REJ09B0288-0150

10.2.2

Standby Control Register 2 (STBCR2)

STBCR2 is an 8-bit readable/writable register that controls the operation of modules in the power-

down mode. This register is initialized to H

′00 at power-on reset but retains the previous value

after manual reset.

Bit

Bit Name

Initial Value

R/W

Description

MSTP10

R/W

Module Stop Bit 10

When the MSTP10 bit is set to 1, the supply of the

clock to the H-UDI is halted.

0: H-UDI runs

1: Clock supply to H-UDI halted

MSTP9

R/W

Module Stop Bit 9

When the MSTP9 bit is set to 1, the supply of the

clock to the UBC is halted.

0: UBC runs

1: Clock supply to UBC halted

MSTP8

R/W

Module Stop Bit 8

When the MSTP8 bit is set to 1, the supply of the

clock to the DMAC is halted.

0: DMAC runs

1: Clock supply to DMAC halted

MSTP7

R/W

Module Stop Bit 7

When the MSTP7 bit is set to 1, the supply of the

clock to the DSP is halted.

0: DSP runs

1: Clock supply to DSP halted

MSTP6

R/W

Module Stop Bit 6

When the MSTP6 bit is set to 1, the supply of the

clock to the TLB is halted.

0: TLB runs

1: Clock supply to TLB halted

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