SH7713 datasheet(343/904 Pages) RENESAS

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Section 10 Power-Down Modes

Rev.1.50 Aug. 30, 2006 Page 303 of 860

REJ09B0288-0150

10.3.2

Software Standby Mode

Transition to Software Standby Mode: The LSI switches from a program execution state to a

software standby mode by executing the SLEEP instruction when the STBY bit is 1 in STBCR. In

a software standby mode, not only the CPU but also the clock and on-chip peripheral modules

halt. The clock output from the CKIO pin also halts.

The contents of the CPU and cache registers remain unchanged. Some registers of on-chip

peripheral modules are, however, initialized. Table 10.3 lists the states of on-chip peripheral

modules registers in software standby mode.

Table 10.3

Module

Registers Initialized

Registers Retaining Data

Interrupt Controller (INTC)

—

All registers

On-Chip Oscillation Circuits

—

All registers

User Break Controller (UBC)

—

All registers

Bus State Controller (BSC)

—

All registers

Timer Unit (TMU)

TSTR

Registers other than TSTR

I/O ports

—

All registers

H-UDI

—

All registers

SCIF0/1

—

All registers

SIOF0/1

—

All registers

EtherC, E-DMAC

—

All registers

DMAC

—

All registers

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