SH7713 datasheet(342/904 Pages) RENESAS

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Section 10 Power-Down Modes

Rev.1.50 Aug. 30, 2006 Page 302 of 860

REJ09B0288-0150

Bit

Bit Name

Initial Value

R/W

Description

MSTP31

R/W

Module Stop Bit 31

When the MSTP31 bit is set to 1, the supply of the

clock to the SCIF1 is halted.

0: The SCIF1 runs

1: Clock supply to the SCIF1 halted

MSTP30

R/W

Module Stop Bit 30

When the MSTP30 bit is set to 1, the supply of the

clock to the SCIF0 is halted.

0: The SCIF0 runs

1: Clock supply to the SCIF0 halted

10.3

Operation

10.3.1

Sleep Mode

Transition to Sleep Mode: Executing the SLEEP instruction when the STBY bit in STBCR is 0

causes a transition from the program execution state to sleep mode. Although the CPU halts

immediately after executing the SLEEP instruction, the contents of its internal registers remain

unchanged. The on-chip peripheral modules continue to run in sleep mode and the clock continues

to be output to the CKIO pin. In sleep mode, a high signal and low signal are output from the

STATUS1 and STATUS0 pins, respectively.

Canceling Sleep Mode: Sleep mode is canceled by an interrupt (NMI, IRQ, IRL, or on-chip

peripheral module) or reset. Interrupts are accepted in sleep mode even when the BL bit in SR is 1.

If necessary, save SPC and SSR to the stack before executing the SLEEP instruction.

• Canceling with an Interrupt

When an NMI, IRQ, IRL, or on-chip peripheral module interrupt occurs, sleep mode is

canceled and interrupt exception handling is executed. A code indicating the interrupt source is

set in INTEVT and INTEVT2.

• Canceling with a Reset

Sleep mode is canceled by a power-on reset or a manual reset.

SH7713 Datasheet(PDF) 342 Page - Renesas Technology Corp