SH7713 datasheet(341/904 Pages) RENESAS

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Section 10 Power-Down Modes

Rev.1.50 Aug. 30, 2006 Page 301 of 860

REJ09B0288-0150

Bit

Bit Name

Initial Value

R/W

Description

MSTP5

R/W

Module Stop Bit 5

When the MSTP5 bit is set to 1, the supply of the

clock to the cache memory is halted.

0: The cache memory runs

1: Clock supply to the cache memory halted



Reserved

This bit is always read as 0. The write value should

always be 0.

MSTP3

R/W

Module Stop Bit 3

When the MSTP3 bit is set to 1, the supply of the

clock to the X/Y memory is halted.

0: The X/Y memory runs

1: Clock supply to the X/Y memory halted

10.2.3

Standby Control Register 3 (STBCR3)

STBCR3 is an 8-bit readable/writable register that controls the operation of the peripheral modules

in the power-down mode. This register is initialized to H

′00 at power-on reset but retains the

previous value after manual reset.

Bit

Bit Name

Initial Value

R/W

Description

7 to 4



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

MSTP33

R/W

Module Stop Bit 33

When the MSTP33 bit is set to 1, the supply of the

clock to the SIOF1 is halted.

0: SIOF1 runs

1: Clock supply to SIOF1 halted

MSTP32

R/W

Module Stop Bit 32

When the MSTP32 bit is set to 1, the supply of the

clock to the SIOF0 is halted.

0: SIOF0 runs

1: Clock supply to SIOF0 halted

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