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SH7713 Datasheet(PDF) 402 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 402 Page - Renesas Technology Corp |
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402 / 904 page  Section 12 Bus State Controller (BSC) Rev.1.50 Aug. 30, 2006 Page 362 of 860 REJ09B0288-0150 • CS6AWCR Bit Bit Name Initial Value R/W Description 31 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 11 SW1 SW0 0 0 R/W R/W Number of Delay Cycles from Address, CSn Assertion to RD, WEn (BEn) Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn (BEn) assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 9 8 7 WR3 WR2 WR1 WR0 1 0 1 0 R/W R/W R/W R/W Number of Access Wait Cycles Specify the number of wait cycles that are necessary for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) |
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