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SH7713 Datasheet(PDF) 403 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 403 Page - Renesas Technology Corp |
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403 / 904 page  Section 12 Bus State Controller (BSC) Rev.1.50 Aug. 30, 2006 Page 363 of 860 REJ09B0288-0150 Bit Bit Name Initial Value R/W Description 6 WM 0 R/W External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 HW1 HW0 0 0 R/W R/W Number of Delay Cycles from RD, WEn (BEn) negation to Address, CSn negation Specify the number of delay cycles from RD and WEn ( BEn) negation to address and CSn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles |
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