SH7713 datasheet(407/904 Pages) RENESAS

407 / 904 page

Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 367 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

SW1

SW0

R/W

Number of Delay Cycles from Address,

CSn Assertion to

RD, WEn (BEn) Assertion

Specify the number of delay cycles from address and

CSn

assertion to

RD and WEn (BEn) assertion. These bits can

be specified only in area 4.

00: 0.5 cycle

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

R/W

Number of Access Wait Cycles

Specify the number of wait cycles to be inserted in the first

read/write access cycle.

0000: 0 cycle

0001: 1 cycle

0010: 2 cycles

0011: 3 cycles

0100: 4 cycles

0101: 5 cycles

0110: 6 cycles

0111: 8 cycles

1000: 10 cycles

1001: 12 cycles

1010: 14 cycles

1011: 18 cycles

1100: 24 cycles

1101: Reserved (setting prohibited)

1110: Reserved (setting prohibited)

1111: Reserved (setting prohibited)

R/W

External Wait Mask Specification

Specifies whether or not the external wait input is valid. The

specification by this bit is valid even when the number of

access wait cycles is 0.

0: External wait is valid

1: External wait is ignored

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