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SH7713 Datasheet(PDF) 408 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 408 Page - Renesas Technology Corp |
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408 / 904 page  Section 12 Bus State Controller (BSC) Rev.1.50 Aug. 30, 2006 Page 368 of 860 REJ09B0288-0150 Bit Bit Name Initial Value R/W Description 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 HW1 HW0 0 0 R/W R/W Number of Delay Cycles from RD, WEn (BEn) negation to Address, CSn negation Specify the number of delay cycles from RD and WEn ( BEn) negation to address and CSn negation. These bits can be specified only in area 4. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles SDRAM*: • CS2WCR Bit Bit Name Initial Value R/W Description 31 to 11 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 1 R Reserved These bits are always read as 1. The write value should always be 1. 9 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 7 A2CL1 A2CL0 1 0 R/W R/W CAS Latency for Area 2 Specify the CAS latency for area 2. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles |
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