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SH7713 Datasheet(PDF) 412 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 412 Page - Renesas Technology Corp |
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412 / 904 page  Section 12 Bus State Controller (BSC) Rev.1.50 Aug. 30, 2006 Page 372 of 860 REJ09B0288-0150 Bit Bit Name Initial Value R/W Description 1 0 TRC1 TRC0 0 0 R/W R/W Number of Idle Cycles from REF Command/Self-refresh Release to ACTV/REF/MRS Command Specify the number of minimum idle cycles between the commands in the following cases. The setting for areas 2 and 3 is common. (1) From issuing the REF command to issuing the ACTV/REF/MSR command (2) From releasing self-refresh to issuing the ACTV/REF/MSR command 00: 2 cycles 01: 3 cycles 10: 5 cycles 11: 8 cycles Note: * If both areas 2 and 3 are specified as SDRAM, TRP1/0, TRCD0/1, TRWL1/0, and TRC1/0 bit settings are common. If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2 as normal space or byte-selection SRAM. |
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