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SH7713 Datasheet(PDF) 410 Page - Renesas Technology Corp

Part # SH7713
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  904 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7713 Datasheet(HTML) 410 Page - Renesas Technology Corp

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Section 12 Bus State Controller (BSC)
Rev.1.50 Aug. 30, 2006 Page 370 of 860
REJ09B0288-0150
Bit
Bit Name
Initial
Value
R/W
Description
11
10
TRCD1
TRCD0
0
1
R/W
R/W
Number of Wait Cycles from ACTV Command to
READ (A)/WRIT (A) Command
Specify the number of minimum wait cycles from issuing
the ACTV command to issuing the READ (A)/WRIT (A)
command. The setting for areas 2 and 3 is common.
00: 0 cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
9
0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
8
7
A3CL1
A3CL0
1
0
R/W
R/W
CAS Latency for Area 3.
Specify the CAS latency for area 3.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
6, 5
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.



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