SH7713 datasheet(404/904 Pages) RENESAS

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Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 364 of 860

REJ09B0288-0150

Burst ROM (Clock Asynchronous):

• CS0WCR

Bit

Bit Name

Initial

Value

R/W

Description

31 to 21



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

BEN

R/W

Burst Enable Specification

Enables or disables 8-burst access for a 16-bit bus width

or 16-burst access for an 8-bit bus width during 16-byte

access. If this bit is set to 1, 2-burst access is performed

four times when the bus width is 16 bits and 4-burst

access is performed four times when the bus width is 8

bits.

To use a device that does not support 8-burst access or

16-burst access, set this bit to 1.

0: Enables 8-burst access for a 16-bit bus width and 16-

burst access for an 8-bit bus width.

1: Disables 8-burst access for a 16-bit bus width and 16-

burst access for an 8-bit bus width.

19, 18



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

BW1

BW0

R/W

Number of Burst Wait Cycles

Specify the number of wait cycles to be inserted between

the second or later access cycles in burst access.

00: 0 cycle

01: 1 cycle

10: 2 cycles

11: 3 cycles

15 to 11



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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