SH7713 datasheet(438/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 398 of 860

REJ09B0288-0150

12.5.4

CSn Assert Period Expansion

The number of cycles from

CSn assertion to RD and WEn (BEn) assertion can be specified by

setting bits SW1 and SW0 in CSnWCR. The number of cycles from

RD and WEn (BEn) negation

CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to

an external device can be obtained. Figure 12.11 shows an example. A Th cycle and a Tf cycle are

added before and after an ordinary cycle, respectively. In these cycles,

RD and WEn (BEn) are not

asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this

prolongation is useful for devices with slow writing operations.

CKIO

A25 to A0

CSn

RD/

D31 to D0

WEn(BEn)

Read

Write

DACKn*

Note: * The waveform for DACKn is when active low is specified.

Figure 12.11

CSn Assert Period Expansion

SH7713 Datasheet(PDF) 438 Page - Renesas Technology Corp