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SH7713 Datasheet(PDF) 442 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 442 Page - Renesas Technology Corp |
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442 / 904 page ![]() Section 12 Bus State Controller (BSC) Rev.1.50 Aug. 30, 2006 Page 402 of 860 REJ09B0288-0150 Table 12.12 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (1)-1 Setting A2/3 BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 11 (32 bits) 00 (11 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Column Address Output Synchronous DRAM Pin Function A17 A25 A17 A16 A24 A16 A15 A23 A15 Unused A14 A22* 2 A22* 2 A12 (BA1)* 3 A13 A21* 2 A21* 2 A11 (BA0) Specifies bank A12 A20 L/H* 1 A10/AP Specifies address/precharge A11 A19 A11 A9 A10 A18 A10 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address |
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