SH7713 datasheet(456/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 416 of 860

REJ09B0288-0150

where the READA command is output to the Td1 cycle where the read data is latched can be

specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0 bits in

CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR and TRCD0 bit in CS3WCR. The number

of cycles from Tc1 to Td1 corresponds to the synchronous DRAM CAS latency. The CAS latency

for the synchronous DRAM is normally defined as up to three cycles. However, the CAS latency

in this LSI can be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a

latch circuit between this LSI and the synchronous DRAM.

Tc4

CKIO

A25 to A0

CSn

RD/

RAS

DQMxx

D31 to D0

Tap

DACKn*2

Tc2

Tc3

Tc1

Td4

Tde

Td2

Td3

Td1

A12/A11*1

CAS

1. Address pin to be connected to the A10 pin of SDRAM.

2. The waveform for DACKn is when active low is specified.

Notes:

Figure 12.14 Burst Read Basic Timing (Auto Precharge)

SH7713 Datasheet(PDF) 456 Page - Renesas Technology Corp