SH7713 datasheet(488/904 Pages) RENESAS

488 / 904 page

Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 448 of 860

REJ09B0288-0150

This LSI

PC card

(memory I/O)

A25 to A0

D7 to D0

CE1

CE2

WE/PGM

IORD

IOWR

REG

A25 to A0

D7 to D0

D15 to D8

RD/

CE1A

CE2A

ICIORD

ICIOWR

I/O Port

WAIT

IOIS16

DIR

D15 to D8

WAIT

IOIS16

CD1,CD2

Card

detection

circuit

Figure 12.38 Example of PCMCIA Interface Connection

Basic Timing for Memory Card Interface: Figure 12.39 shows the basic timing of the PCMCIA

IC memory card interface. If areas 5 and 6 in the physical space are specified as the PCMCIA

interface, accessing the common memory areas in areas 5 and 6 automatically accesses the IC

memory card interface. If the external bus frequency (CKIO) increases, the setup times and hold

times for the address pins (A25 to A0) to RD and WE, card enable signals (

CE1A, CE2A, CE1B,

CE2B), and write data (D15 to D0) become insufficient. To prevent this error, the LSI can specify

the setup times and hold times for areas 5 and 6 in the physical space independently, using

CS5BWCR and CS6BWCR. In the PCMCIA interface, as in the normal space interface, a

software wait or hardware wait can be inserted using the WAIT pin. Figure 12.40 shows the

PCMCIA memory bus wait timing.

SH7713 Datasheet(PDF) 488 Page - Renesas Technology Corp

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