SH7713 datasheet(491/904 Pages) RENESAS

491 / 904 page

Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 451 of 860

REJ09B0288-0150

If the PCMCIA card is accessed as an I/O card in little endian mode, dynamic bus sizing for the

I/O bus can be achieved using the

IOIS16 signal. If the IOIS16 signal is brought high in a word-

size I/O bus cycle while the bus width of area 6 is specified as 16 bits, the bus width is recognized

as 8 bits and data is accessed twice in 8-bit units in the I/O bus cycle to be executed.

The

IOIS16 signal is sampled at the falling edge of CKIO in the Tpci0, Tpci0w, and Tpci1 cycles

when the TED[3:0] bits are specified as 1.5 cycles or more, and is reflected in the CE2 signal 1.5

cycles after the CKIO sampling point. The TED[3:0] bits must be specified appropriately to satisfy

the setup time from

ICIORD and ICIOWR of the PC card to CEn.

Figure 12.44 shows the dynamic bus sizing basic timing.

Note that the

IOIS16 signal is not supported in big endian mode. In the big endian mode, the

IOIS16 signal must be fixed low.

Tpci1w

CKIO

A25 to A0

CExx

RD/

ICIORD

D15 to D0

ICIOWR

D15 to D0

Read

Write

Tpci2

Tpci1

Tpci1w

Figure 12.42 Basic Timing for PCMCIA I/O Card Interface

SH7713 Datasheet(PDF) 491 Page - Renesas Technology Corp