SH7713 datasheet(493/904 Pages) RENESAS

493 / 904 page

Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 453 of 860

REJ09B0288-0150

12.5.9

Burst ROM (Clock Synchronous) Interface

The burst ROM (clock synchronous) interface is supported to access a ROM with a synchronous

burst function at high speed. The burst ROM interface accesses the burst ROM in the same way as

a normal space. This interface is valid only for area 0.

In the first access cycle, wait cycles are inserted. In this case, the number of wait cycles to be

inserted is specified by the W[3:0] bits of the CS0WCR. In the second and subsequent cycles, the

number of wait cycles to be inserted is specified by the BW[1:0] bits of the CS0WCR.

While the burst ROM is accessed (clock synchronous), the

BS signal is asserted only for the first

access cycle and an external wait input is also valid for the first access cycle.

If the bus width is 16 bits, the burst length must be specified as 8. If the bus width is 32 bits, the

burst length must be specified as 4. The burst ROM interface does not support the 8-bit bus width

for the burst ROM. The burst ROM interface performs burst operations for all read accesses. For

example, in a longword access over a 16-bit bus, valid 16-bit data is read two times and invalid

16-bit data is read six times.

These invalid data read cycles increase the memory access time and degrade the program

execution speed and DMA transfer speed. To prevent this problem, a 16-byte read by cache fill or

16-byte read by the DMA should be used. The burst ROM interface performs write accesses in the

same way as normal space access.

Note:

The burst ROM (clock synchronous) must be accessed as cacheable space.

Twb

CKIO

Address

Note: The waveform for DACKn is when active low is specified.

CSn

RD/

D15 to D0

DACKn*

T2B

Twb

T2B

Twb

T2B

Twb

T2B

Twb

WAIT

Figure 12.45 Burst ROM (Clock Synchronous) Access Timing

(Burst Length = 8, Wait Cycles inserted in First Access = 2,

Wait Cycles inserted in Second and Subsequent Accesses = 1)

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