SH7713 datasheet(496/904 Pages) RENESAS

496 / 904 page

Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 456 of 860

REJ09B0288-0150

while the SDRAM waits for the refresh. The LSI asserts the

REFOUT pin until the bus mastership

is received. If the slave releases the bus, the LSI acquires the bus mastership to execute the

SDRAM refresh.

The bus release by the

BREQ and BACK signal handshaking requires some overhead. If the slave

has many tasks, multiple bus cycles should be executed in a bus mastership acquisition. Reducing

the cycles required for master to slave bus mastership transitions streamlines the system design.

CKIO

A25 to A0

CSn

Other bus

control signals

D31 to D0

BREQ

BACK

Figure 12.46 Bus Arbitration Timing

12.5.12

Others

Reset: The bus state controller (BSC) can be initialized completely only at power-on reset. At

power-on reset, all signals are negated and output buffers are turned off regardless of the bus cycle

state. All control registers are initialized. In standby, sleep, and manual reset, control registers of

the bus state controller are not initialized. At manual reset, the current bus cycle being executed is

completed and then the access wait state is entered. If a 16-byte transfer is performed by a cache

or if another LSI on-chip bus master module is executed when a manual reset occurs, the current

access is cancelled in longword units because the access request is cancelled by the bus master at

manual reset. If a manual reset is requested during cache fill operations, the contents of the cache

cannot be guaranteed. Since the RTCNT continues counting up during manual reset signal

assertion, a refresh request occurs to initiate the refresh cycle. Note, however, a bus arbitration

request by the

BREQ signal can’t be accepted during manual reset signal assertion.

Some flash memories may specify a minimum time from reset release to the first access. To

ensure this minimum time, the bus state controller supports a 5-bit reset wait counter (RWTCNT).

At power-on reset, the RWTCNT is cleared to 0. After a power-on reset, RWTCNT is counted up

synchronously together with CKIO and an external access will not be generated until RWTCNT is

counted up to H

′007F. At a manual reset, RWTCNT is not cleared. RWTCNT cannot be read from

or written to.

SH7713 Datasheet(PDF) 496 Page - Renesas Technology Corp