SH7713 datasheet(499/904 Pages) RENESAS

499 / 904 page

Section 13 Direct Memory Access Controller (DMAC)

Rev.1.50 Aug. 30, 2006 Page 459 of 860

REJ09B0288-0150

Section 13 Direct Memory Access Controller (DMAC)

The direct memory access controller (DMAC) can be used in place of the CPU to perform high-

speed transfers between external devices that have DACK (transfer request acknowledge signal),

external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral

modules.

13.1

Features

• Six channels (Two channels can receive an external request)

• 4-Gbyte physical address space

• Data transfer unit is selectable: Byte, Word (two bytes), Longword (four bytes), and 16 bytes

(longword

× 4)

• Maximum transfer count: 16,777,216 transfers (24 bits)

• Address mode: Dual address mode and single address mode are supported.

• Transfer requests:

An external request, on-chip peripheral module request, or auto request can be selected.

The following modules can issue an on-chip peripheral module request.

SCIF0, SCIF1, SIOF0, SIOF1

• Bus mode: Cycle steal mode or burst mode can be selected.

• Channel priority levels: The channel priority levels are selectable between fixed mode and

round-robin mode.

• Interrupt request: An interrupt request can be generated to the CPU at the end of the specified

counts of data transfer.

• External request detection: There are following four types of DREQ input detection.

Low-level detection

High-level detection

Rising-edge detection

Falling-edge detection

• Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND

can be set independently.

SH7713 Datasheet(PDF) 499 Page - Renesas Technology Corp