SH7713 datasheet(498/904 Pages) RENESAS

498 / 904 page

Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 458 of 860

REJ09B0288-0150

In write-through mode, the cache is first searched. If data is detected at the address corresponding

to the cache, the data is re-written to the cache simultaneously with the actual write via the internal

bus. If data is not detected at the address corresponding to the cache, the cache is not modified but

an actual write is performed via the internal bus.

Since the bus state controller (BSC) incorporates a one-stage write buffer, the BSC can execute an

access via the internal bus before the previous external bus cycle is completed in a write cycle. If

the on-chip module is read or written after the external low-speed memory is written, the on-chip

module can be accessed before the completion of the external low-speed memory write cycle.

In read cycles, the CPU is placed in the wait state until read operation has been completed. To

continue the process after the data write to the device has been completed, perform a dummy read

to the same address to check for completion of the write before the next process to be executed.

The write buffer of the BSC functions in the same way for an access by a bus master other than

the CPU such as the DMAC or E-DMAC. Accordingly, to perform dual address DMA transfers,

the next read cycle is initiated before the previous write cycle is completed. Note, however, that if

both the DMA source and destination addresses exist in external memory space, the next write

cycle will not be initiated until the previous write cycle is completed.

On-Chip Peripheral Module Access: To access an on-chip module register, two or more

peripheral module clock (P

φ) cycles are required. Care must be taken in system design.

SH7713 Datasheet(PDF) 498 Page - Renesas Technology Corp