SH7713 datasheet(495/904 Pages) RENESAS

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Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 455 of 860

REJ09B0288-0150

signal or other bus control signals. The states that do not allow bus mastership release are shown

below.

1. 16-byte transfer because of a cache miss

2. During copyback operation for the cache

3. Between the read and write cycles of a TAS instruction

4. Multiple bus cycles generated when the data bus width is smaller than the access size (for

example, between bus cycles when longword access is made to a memory with a data bus

width of 8 bits)

5. 16-byte transfer by the DMAC or E-DMAC

6. Setting the BLOCK bit in CMNCR to 1

Bits DPRTY[1:0] in CMNCR can select whether or not the bus request is received during DMAC

burst transfer.

This LSI has the bus mastership until a bus request is received from another device. Upon

acknowledging the assertion (low level) of the external bus request signal

BREQ, the LSI releases

the bus at the completion of the current bus cycle and asserts the

BACK signal. After the LSI

acknowledges the negation (high level) of the

BREQ signal that indicates the slave has released

the bus, it negates the

BACK signal and resumes the bus usage.

The SDRAM issues a all bank precharge command (PALL) when active banks exist and releases

the bus after completion of a PALL command.

The bus sequence is as follows. The address bus and data bus are placed in a high-impedance state

synchronized with the rising edge of CKIO. The bus mastership enable signal is asserted 0.5

cycles after the above timing, synchronized with the falling edge of CKIO. The bus control signals

(

BS, CSn, RAS, CAS, DQMxx, WEn (BEn), RD, and RD/WR) are placed in the high-impedance

state at subsequent rising edges of CKIO. Bus request signals are sampled at the falling edge of

CKIO.

The sequence for reclaiming the bus mastership from a slave is described below. 1.5 cycles after

the negation of

BREQ is detected at the falling edge of CKIO, the bus control signals are driven

high. The

BACK is negated at the next falling edge of the clock. The fastest timing at which actual

bus cycles can be resumed after bus control signal assertion is at the rising edge of the CKIO

where address and data signals are driven. Figure 12.46 shows the bus arbitration timing.

In an original slave device designed by the user, multiple bus accesses are generated continuously

to reduce the overhead caused by bus arbitration. In this case, to execute SDRAM refresh

correctly, the slave device must be designed to release the bus mastership within the refresh

interval time. To achieve this, the LSI instructs the

REFOUT pin to request the bus mastership

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