SH7713 datasheet(774/904 Pages) RENESAS

774 / 904 page

Section 22 User Debugging Interface (H-UDI)

Rev.1.50 Aug. 30, 2006 Page 734 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

15 to 13

TI7 to TI5

All 1

TI4

11 to 8

TI3 to TI0

All 1

Test Instruction 7 to 0

The H-UDI instruction is transferred to SDIR by a

serial input from TDI.

For commands, see Table 22.2.

7 to 2



All 1

Reserved

These bits are always read as 1.



Reserved

This bit is always read as 0.



Reserved

This bit is always read as 1.

Table 22.2

H-UDI Commands

Bits 15 to 8

TI7

TI6

TI5

TI4

TI3

TI2

TI1

TI0

Description

—

JTAG EXTEST

—

JTAG CLAMP

—

JTAG HIGHZ

—

JTAG SAMPLE/PRELOAD

—

H-UDI reset negate

—

H-UDI reset assert

—

H-UDI interrupt

—

JTAG IDCODE (Initial value)

—

JTAG BYPASS

Other than the above

Reserved

22.3.3

Boundary Scan Register (SDBSR)

SDBSR is a shift register, located on the PAD, for controlling the input/output pins of this LSI.

The initial value is undefined. SDBSR cannot be accessed by the CPU.

Using the EXTEST, SAMPLE/PRELOAD, CLAMP, and HIGHZ commands, a boundary scan

test conforming to the JTAG standard can be carried out. Table 22.3 shows the correspondence

between this LSI’s pins and boundary scan register bits.

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