SH7713 datasheet(772/904 Pages) RENESAS

772 / 904 page

Section 22 User Debugging Interface (H-UDI)

Rev.1.50 Aug. 30, 2006 Page 732 of 860

REJ09B0288-0150

22.2

Input/Output Pins

Table 22.1 shows the pin configuration of the H-UDI.

Table 22.1

Pin Configuration

Pin Name

Input/Output

Description

TCK

Input

Serial Data Input/Output Clock Pin

Data is serially supplied to the H-UDI from the data input pin

(TDI), and output from the data output pin (TDO), in

synchronization with this clock.

TMS

Input

Mode Select Input Pin

The state of the TAP control circuit is determined by changing

this signal in synchronization with TCK. The protocol conforms

to the JTAG standard (IEEE Std.1149.1).

TRST

Input

Reset Input Pin

Input is accepted asynchronously with respect to TCK, and

when low, the H-UDI is reset.

TRST must be low for a constant

period when power is turned on regardless of using the H-UDI

function. As the same as the

RESETP pin, the TRST pin should

be driven low at the power-on reset state and driven high after

the power-on reset state is released. This is different from the

JTAG standard.

See section 22.4.2, Reset Configuration, for more information.

TDI

Input

Serial Data Input Pin

Data transfer to the H-UDI is executed by changing this signal

in synchronization with TCK.

TDO

Output

Serial Data Output Pin

Data read from the H-UDI is executed by reading this pin in

synchronization with TCK. The data output timing depends on

the command type set in the SDIR. See section 22.4.3 TDO

Output Timing, for more information.

ASEMD0

Input

ASE Mode Select Pin

If a low level is input at the

ASEMD0 pin while the RESETP pin

is asserted, ASE mode is entered; if a high level is input,

normal mode is entered. In ASE mode, dedicated emulator

function can be used. The input level at the

ASEMD0 pin

should be held for at least one cycle after

RESETP negation.

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