SH7713 datasheet(768/904 Pages) RENESAS

768 / 904 page

Section 21 I/O Ports

Rev.1.50 Aug. 30, 2006 Page 728 of 860

REJ09B0288-0150

Table 21.1

Port A Data Register (PADR) Read/Write Operations

PAnMD1 PAnMD0 Pin State

Read

Write

Other function

PADR value

Value is written to PADR, but does not

affect pin state.

Output

PADR value

Write value is output from pin.

Input (Pull-up

MOS on)

Pin state

Value is written to PADR, but does not

affect pin state.

Input (Pull-up

MOS off)

Pin state

Value is written to PADR, but does not

affect pin state.

[Legend]

n = 0 to 7

21.2.2

Port B Data Register (PBDR)

PBDR is an 8-bit readable/writable register that stores the data for pins PTB7 to PTB0. Bits

PB7DT to PB0DT correspond to the pins PTB7 to PTB0. PBDR is initialized to H

′00 by a power-

on reset but is not initialized by a manual reset, in standby mode, or sleep mode.

Bit

Bit Name

Initial

Value

R/W

Description

PB7DT

R/W

PB6DT

R/W

PB5DT

R/W

PB4DT

R/W

PB3DT

R/W

PB2DT

R/W

PB1DT

R/W

PB0DT

R/W

When the pin function is general output port, if the port

is read, the value of the corresponding PBDR bit is

returned directly. When the function is general input

port, if the port is read, the corresponding pin level is

read. Tables 21.2 and 21.3 show the function of

PBDR.

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