SH7713 datasheet(767/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 21 I/O Ports

Rev.1.50 Aug. 30, 2006 Page 727 of 860

REJ09B0288-0150

Section 21 I/O Ports

21.1

Overview

This LSI has three 8-bit ports (ports A to C). All port pins are multiplexed with other pin functions

(the pin function controller (PFC) handles the selection of pin functions and pull-up MOS control).

Each port has a data register which stores data for the pins.

21.2

21.2.1

Port A Data Register (PADR)

PADR is an 8-bit readable/writable register that stores data for pins PTA7 to PTA0. Bits PA7DT

to PA0DT correspond to pins PTA7 to PTA0. PADR is initialized to H

′00 by a power-on reset but

is not initialized by a manual reset, in standby mode, or sleep mode.

Bit

Bit Name

Initial

Value

R/W

Description

PA7DT

R/W

PA6DT

R/W

PA5DT

R/W

PA4DT

R/W

PA3DT

R/W

PA2DT

R/W

PA1DT

R/W

PA0DT

R/W

When the pin function is general output port, if the port

is read, the value of the corresponding PADR bit is

returned directly. When the function is general input

port, if the port is read, the corresponding pin level is

read. Table 21.1 shows the function of PADR.

SH7713 Datasheet(PDF) 767 Page - Renesas Technology Corp

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