SH7713 datasheet(773/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 22 User Debugging Interface (H-UDI)

Rev.1.50 Aug. 30, 2006 Page 733 of 860

REJ09B0288-0150

Pin Name

Input/Output

Description

ASEBRKAK

AUDSYNC

AUDATA3 to 0

AUDCK

Output

Dedicated emulator pin

22.3

The H-UDI has the following registers. Refer the section 23, List of Registers, for the addresses

and access size for registers.

• Bypass register (SDBPR)

• Instruction register (SDIR)

• Boundary scan register (SDBSR)

• ID register (SDID)

22.3.1

Bypass Register (SDBPR)

SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to the bypass

mode, SDBPR is connected between H-UDI pins TDI and TDO. The initial value is undefined but

SDBPR is initialized to 0 if the TAP is in Capture-DR state.

22.3.2

Instruction Register (SDIR)

SDIR is a 16-bit read-only register. The register is in JTAG IDCODE in its initial state. It is

initialized by

TRST assertion or in the TAP test-logic-reset state, and can be written to by the H-

UDI irrespective of the CPU mode. Operation is not guaranteed if a reserved command is set in

this register.

SH7713 Datasheet(PDF) 773 Page - Renesas Technology Corp