SH7713 datasheet(833/904 Pages) RENESAS

833 / 904 page

Section 24 Electrical Characteristics

Rev.1.50 Aug. 30, 2006 Page 793 of 860

REJ09B0288-0150

24.3.2

Control Signal Timing

Table 24.6

Control Signal Timing

(Conditions: V

CCQ = VCCQ-RTC = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V,

SSQ = VSS = VSSQ-RTC = VSS-PLL1 = VSS-PLL2 = 0 V, Ta = –20 to 75°C)

66.67 MHz*

Item

Symbol

Min.

Max.

Unit

Figure

RESETP pulse width

RESPW

20*

—

cyc

24.12

RESETP setup time*1

RESPS

—

RESETM pulse width

RESMW

20*

—

cyc

RESETM setup time

RESMS

—

BREQ setup time

BREQS

1/2 t

cyc+10

—

24.14

BREQ hold time

BREQH

1/2 t

cyc+3

—

NMI setup time*

NMIS

—

24.13

NMI hold time

NMIH

—

IRQ5 to IRQ0 setup time*

IRQS

—

IRQ5 to IRQ0 hold time

IRQH

—

BACK delay time

BACKD

—

1/2 t

cyc+13

24.14

STATUS1, STATUS0 delay time

STD

—

24.15

IRQOUT delay time

IRQOTD

—

1/2 t

cyc+12

24.16

Bus tri-state delay time 1

BOFF1

24.14,

Bus tri-state delay time 2

BOFF2

24.15

Bus buffer-on time 1

BON1

Bus buffer-on time 2

BON2

Notes: t

cyc is the external bus clock cycle (B clock cycle).

RESETP, NMI, and IRQ5 to IRQ0 are asynchronous. Changes are detected at the

clock rise when the setup shown is kept. When the setup cannot be kept, detection can

be delayed until the next clock rises.

2. The upper limit of the external bus clock is 66.67 MHz.

3. In standby mode, t

RESPW = tOSC2 (10 ms). When the crystal oscillation continues or the

clock multiplication ratio is changed in standby mode, t

RESPW = tPLL1 (100 µs).

4. In standby mode, t

RESMW = tOSC2 (10 ms). When the crystal oscillation continues or the

clock multiplication ratio is changed in standby mode,

RESETM must be kept low until

STATUS (0-1) changes to reset (HH).

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