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SH7713 Datasheet(PDF) 122 Page - Renesas Technology Corp

Part # SH7713
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  904 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7713 Datasheet(HTML) 122 Page - Renesas Technology Corp

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Section 3 DSP Operating Unit
Rev.1.50 Aug. 30, 2006 Page 82 of 860
REJ09B0288-0150
The rule is shown in table 3.3.
Table 3.3
RS and RE Setting Rule
Number of Instructions in Repeat Loop
1
2
3
≥ 4
RS
RptStart0 + 8
RptStart0 + 6
RptStart0 + 4
RptStart
RE
RptStart0 + 4
RptStart0 + 4
RptStart0 + 4
RptEnd3 + 4
Note:
The terms used above in table 3.3, are defined as follows.
RptStart: Address of the repeat start instruction
RptStart0: Address of the instruction one instruction prior to the repeat start instruction
RptEnd3: Address of the instruction three instructions prior to the repeat end instruction
Repeat Control Instructions and Repeat Control Macros: To describe a repeat loop, the RS
and RE registers must be specified appropriately by the LDRS and LDRS instructions and then the
number of repetitions must be specified by the SERTC instruction. An 8-bit immediate data or a
general register can be used as an operand of the SETRC instruction. To specify the RC as a value
greater than 256, use SETRC Rm type instructions.
Table 3.4
Repeat Control Instructions
Instruction
Operation
Number of
Execution States
LDRS @(disp,PC)
Calculates (disp x 2 + PC) and stores the result to the
RS register
1
LDRE @(disp,PC)
Calculates (disp x 2 + PC) and stores the result to the
RE register
1
SETRC #imm
Sets 8-bit immediate data imm to the RC[11:0] bits of
the SR register and sets the information related to the
number of repetitions to the RF[1:0] bits of the SR.
RC[11:0] can be specified as 0 to 255.
1
SETRC Rm
Sets the[11:0] bits of the Rm register to the RC[11:0]
bits of the SR register and sets the information related
to the number of repetitions to the RF[1:0] bits of the
SR.
RC[11:0] can be specified as 0 to 4095.
1
The RS and RE registers must be specified appropriately according to the rules shown in table 3.3.
The SH assembler supports control macros (REPEAT) as shown in table 3.5 to solve problems.



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