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SH7713 Datasheet(PDF) 125 Page - Renesas Technology Corp

Part # SH7713
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  904 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7713 Datasheet(HTML) 125 Page - Renesas Technology Corp

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Section 3 DSP Operating Unit
Rev.1.50 Aug. 30, 2006 Page 85 of 860
REJ09B0288-0150
Restrictions on Repeat Loop Control
1. Repeat control instruction assignment
The SETRC instruction must be executed after executing the LDRS and LDRE instructions. In
addition, note that at least one instruction is required between the SETRC instruction and a
repeat start instruction.
2. Illegal instruction one or more instructions following the repeat detection instruction
If one of the following instructions is executed between an instruction following a repeat
detection instruction to a repeat end instruction, an illegal instruction exception occurs.
 Branch instructions
BRA, BSR, BT, BF, BT/F, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA
 Repeat control instructions
SETRC, LDRS, LDRE
 Load instructions for SR, RS, and RE registers
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS
Note:
This restriction applies to all instructions for a repeat loop consisting of one to three
instructions and to three instructions including a repeat end instruction for a repeat loop
consisting of four or more instructions.
3. Instructions prohibited during repeat loop (In a repeat loop consisting of four or more
instructions)
The following instructions must not be placed between the repeat start instruction and repeat
detection instruction in a repeat loop consisting of four or more instructions. Otherwise, the
correct operation cannot be guaranteed.
 Repeat control instructions
SETRC, LDRS, LDRE
 Load instructions for SR, RS, and RE registers
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS
Note:
Multiple repeat loops cannot be guaranteed. Describe the inner loop by repeat control
instructions, and the external loop by other instructions such as DT or BF/S.
4. Restriction on branching to an instruction following the repeat detection instruction and an
exception acceptance



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