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SH7713 Datasheet(PDF) 196 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 196 Page - Renesas Technology Corp |
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196 / 904 page  Section 4 Exception Handling Rev.1.50 Aug. 30, 2006 Page 156 of 860 REJ09B0288-0150 Figure 4.1 shows the bit configuration of each register. 31 TRA EXPEVT INTEVT INTEVT2 TRA EXPEVT INTEVT INTEVT2 TEA TEA 10 9 2 1 0 31 12 11 0 0 0 0 0 0 31 12 11 0 31 12 11 0 31 0 Figure 4.1 Register Bit Configuration 4.1.1 TRAPA Exception Register (TRA) TRA is assigned to address H ′FFFFFFD0 and consists of the 8-bit immediate data (imm) of the TRAPA instruction. TRA is automatically specified by the hardware when the TRAPA instruction is executed. Only bits 9 to 2 of the TRA can be re-written using the software. Bit Bit Name Initial Value R/W Description 31 to 10 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 2 TRA R/W 8-bit Immediate Data 1, 0 R Reserved These bits are always read as 0. The write value should always be 0. |
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