SH7713 datasheet(198/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 4 Exception Handling

Rev.1.50 Aug. 30, 2006 Page 158 of 860

REJ09B0288-0150

4.1.4

Interrupt Event Register 2 (INTEVT2)

INTEVT2 is assigned to address H

′A4000000 and consists of the exception code. Exception codes

to be specified in INTEVT2 are those for interrupt requests. These exception codes are

automatically specified by the hardware when an exception occurs. INTEVT2 cannot be modified

using the software.

Bit

Bit Name

Initial Value

R/W

Description

31 to 12



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

11 to 0

INTEVT2



12-bit Exception Code

4.1.5

Exception Address Register (TEA)

TEA is assigned to address H

′FFFFFFFC and the logical address for an exception occurrence is

stored in this register when an exception related to memory accesses occurs. TEA can be modified

using the software.

Bit

Bit Name

Initial Value

R/W

Description

31 to 0

TEA

R/W

Logical address for Exception Occurrence

SH7713 Datasheet(PDF) 198 Page - Renesas Technology Corp