SH7713 datasheet(199/904 Pages) RENESAS

199 / 904 page

Section 4 Exception Handling

Rev.1.50 Aug. 30, 2006 Page 159 of 860

REJ09B0288-0150

4.2

Exception Handling Function

4.2.1

Exception Handling Flow

In exception handling, the contents of the program counter (PC) and status register (SR) are saved

in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of

the exception handler is invoked from a vector address. By executing the return from exception

handler (RTE) in the exception handler routine, it restores the contents of PC and SR, and returns

to the processor state at the point of interruption and the address where the exception occurred.

A basic exception handling sequence consists of the following operations. If an exception occurs

and the CPU accepts it, operations 1 to 8 are executed.

The contents of PC is saved in SPC.

The contents of SR is saved in SSR.

The block (BL) bit in SR is set to 1, masking any subsequent exceptions.

The mode (MD) bit in SR is set to 1 to place the privileged mode.

The register bank (RB) bit in SR is set to 1.

An exception code identifying the exception event is written to bits 11–0 of the exception

event (EXPEVT) or interrupt event (INTEVT or INTEVT2) register.

If a TRAPA instruction is executed, an 8-bit immediate data specified by the TRAPA

instruction is set to TRA. For an exception related to memory accesses, the logic address

where the exception occurred is written to TEA. *

Instruction execution jumps to the designated exception vector address to invoke the handler

routine.

The above operations from 1 to 8 are executed in sequence. During these operations, no other

exceptions may be accepted unless multiple exception acceptance is enabled.

In an exception handling routine for a general exception, the appropriate exception handling must

be executed based on an exception source determined by the EXPEVP. In an interrupt exception

handling routine, the appropriate exception handling must be executed based on an exception

source determined by the INTEVT or INTEVT2. After the exception handling routine has been

completed, program execution can be resumed by executing an RTE instruction. The RTE

instruction causes the following operations to be executed.

The contents of the SSR are restored into the SR to return to the processing state in effect

before the exception handling took place.

A delay slot instruction of the RTE instruction is executed.*

SH7713 Datasheet(PDF) 199 Page - Renesas Technology Corp