SH7713 datasheet(203/904 Pages) RENESAS

203 / 904 page

Section 4 Exception Handling

Rev.1.50 Aug. 30, 2006 Page 163 of 860

REJ09B0288-0150

Table 4.1

Exception Event Vectors

Exception Type

Current

Instruction

Exception Event

Priority*

Exception

Order

Process

at BL=1

Vector

Code

Vector Offset

Power-on reset

—

Reset

H'000

—

Manual reset

—

Reset

H'020

—

Reset

(asynchronous)

Aborted

H-UDI reset

Reset

H'000

—

User break(before

instruction execution)

Ignored

H'1E0

H'00000100

Re-executed

CPU address error

(instruction access) *

Reset

H'0E0

H'00000100

TLB miss (instruction

access) *

1-1

Reset

H'040

H'00000400

TLB invalid

(instruction access)*

1-2

Reset

H'040

H'00000100

TLB protection

violation

(instruction access)*

1-3

Reset

H'0A0

H'00000100

Illegal general instruction

exception

Reset

H'180

H'00000100

Illegal slot

instruction exception

Reset

H'1A0

H'00000100

Completed

Unconditional trap

(TRAPA instruction)

Reset

H'160

H'00000100

Re-executed

CPU address error

(data read/write)*

Reset

H'0E0/

H’100

H'00000100

TLB miss (data

read/write)*

3-1

Reset

H'040/

H’060

H'00000400

TLB invalid (data

read/write)*

3-2

Reset

H'040/

H’060

H'00000100

General exception

events

(synchronous)

TLB protection

violation (data

read/write)*

3-3

Reset

H'0A0/

H’0C0

H'00000100

Initial page write

(data write)*

3-4

Reset

H'080

H'00000100

Completed

User breakpoint (After

instruction execution,

address)

Ignored

H'1E0

H'00000100

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