SH7713 datasheet(206/904 Pages) RENESAS

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Section 4 Exception Handling

Rev.1.50 Aug. 30, 2006 Page 166 of 860

REJ09B0288-0150

4.3.2

General Exceptions

CPU address error:

• Conditions

 Instruction is fetched from odd address (4n + 1, 4n + 3)

 Word data is accessed from addresses other than word boundaries (4n + 1, 4n + 3)

 Longword is accessed from addresses other than longword boundaries (4n + 1, 4n + 2,

4n + 3)

 The area ranging from H'80000000 to H'FFFFFFFF in logical space is accessed in user

mode

• Types

Instruction synchronous, re-execution type

• Save address

Instruction fetch: An instruction address to be fetched when an exception occurred

Data access: An instruction address where an exception occurs (a delayed branch instruction

address if an instruction is assigned to a delay slot)

• Exception code

An exception occurred during read: H

′0E0

An exception occurred during write: H

′100

• Remarks

The logical address (32 bits) that caused the exception is set in TEA.

Illegal general instruction exception:

• Conditions

 When undefined code not in a delay slot is decoded

Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S

Note:

For details on undefined code, refer to table 2.12 in section 2, CPU. When an undefined

code other than H

′FC00 to H′FFFF is decoded, operation cannot be guaranteed.

 When a privileged instruction not in a delay slot is decoded in user mode

Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR

with LDC/STC are not privileged instructions.

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