SH7713 datasheet(207/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 4 Exception Handling

Rev.1.50 Aug. 30, 2006 Page 167 of 860

REJ09B0288-0150

• Types

Instruction synchronous, re-execution type

• Save address

An instruction address where an exception occurs

• Exception code

′180

• Remarks

None

Illegal slot instruction:

• Conditions

 When undefined code in a delay slot is decoded

Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S

 When a privileged instruction in a delay slot is decoded in user mode

Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR

with LDC/STC are not privileged instructions.

 When an instruction that rewrites PC in a delay slot is decoded

Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,

BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR

• Types

Instruction synchronous, re-execution type

• Save address

A delayed branch instruction address

• Exception code

′1A0

• Remarks

None

SH7713 Datasheet(PDF) 207 Page - Renesas Technology Corp