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SH7713 Datasheet(PDF) 211 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 211 Page - Renesas Technology Corp |
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211 / 904 page  Section 4 Exception Handling Rev.1.50 Aug. 30, 2006 Page 171 of 860 REJ09B0288-0150 • Save address Instruction fetch: An instruction address to be fetched when an exception occurred Data access: An instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) • Exception code An exception occurred during read: H ′0A0 An exception occurred during write: H ′0C0 • Remarks The logical address (32 bits) that caused the exception is set in TEA and the MMU registers are updated. Initial page write exception: • Conditions A hit occurred to the TLB for a data write access, but D = 0. • Types Instruction synchronous, re-execution type • Save address Instruction fetch: An instruction address to be fetched when an exception occurred Data access: An instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) • Exception code H ′080 • Remarks The logical address (32 bits) that caused the exception is set in TEA and the MMU registers are updated. |
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